The present invention is adapted for use in computer systems and, more particularly, is an improved address translation apparatus for translating virtual addresses into real addresses utilizing random access memory and substitute paging.
The invention provides an apparatus improvement for maximizing system performance on all virtual memory operations which require address translation prior to initiating real memory access. Medium to large scale computer systems utilize a virtual memory concept, in one form or another, to maximize the efficiency of the single most expensive component in the processing unit, the memory storage element. Generally, for performance reasons, at least some part of the storage element is implemented using semiconductor memory chips. Currently, the most popular memory chips are the dynamic random access memories, DRAM's, since they afford high densities (up to 65,536 bits per chip), good performance and they are reasonably priced compared to alternate technologies. The amount of physical memory provided in an actual system will be restricted due to cost, power, packaging and/or other considerations.
Virtual memory storage allows software programs to be written and executed on a system using an address space that is greater than the actual physically addressable memory used in the system. This is possible because additional memory (slower speed) is provided by way of disc storage, tape, cards, etc. The additional or bulk storage memory, stores pages of information which can be transferred when needed into the computer's higher speed memory to effectively increase the working size of the computer's memory.
Memory management resources map sections of a user's program in groups of bytes (8 bits), often referred to as pages, into the physical memory as required. Once the page is in memory, the data on that page can be accessed provided that some element within the processor can remember the mapping function between the virtual address and the real (physical) memory address. For performance reasons, the mapping function is most frequently implemented in hardware. Unless exotic hardware techniques are employed, this mapping, or address translation operation as it is also known, is never accomplished in zero time. The actual overhead in the system may be as much as 1/2 of the time it would otherwise take to access memory in a non-translation mode. In conventional hardware implementations memory access time using address translation would be calculated by summing the amount of time it takes to convert a virtual address to a real address with the amount of time it takes to perform the actual memory operation.
It therefore is highly desirable to decrease the amount of time allocated to address translation without substantially increasing the costs associated with such a decrease. The present invention provides a unique implementation for minimizing the address translation time.